1. Field of the Invention
The present invention relates to a display device and method of manufacturing a display device, and more particularly, to a liquid crystal display device and method of manufacturing a liquid crystal display device.
2. Discussion of the Related Art
Among the various flat display devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, electroluminescent display (ELD) devices, and vacuum fluorescent display (VFD) devices, the liquid crystal display (LCD) devices have been most commonly used because of their thin profile, light weight, and low power consumption. Accordingly, the LCD devices are commonly substituted for Cathode Ray Tube (CRT) devices. In addition, in mobile type LCD devices, such as a display for a notebook computer, the LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
Despite various technical developments within the LCD technologies, enhancement of picture quality of the LCD devices has been lacking. Accordingly, in order to incorporate the LCD devices into general display devices, high quality picture, such as high resolution and high luminance in large-sized display screens, must be achieved while maintaining the light weight, thin profile, and low power consumption.
A common LCD device includes an LCD panel for displaying a picture image, and a driving part for supplying a driving signal to the LCD panel. The LCD panel includes lower and upper glass substrates bonded to each other at predetermined intervals, and a liquid crystal material layer injected between the lower and upper glass substrates.
The lower substrate (TFT array substrate) includes a plurality of gate lines arranged along a first direction at fixed intervals, a plurality of data lines arranged along a second direction at fixed intervals perpendicular to the first direction, a plurality of pixel electrodes formed in a matrix configuration in pixel regions defined by intersections of the plurality of gate and data lines, and a plurality of switching thin film transistors responsive to signals of the gate lines for transmitting signals of the data lines to the pixel electrodes. In addition, the upper substrate (color filter array substrate) includes a black matrix layer for preventing light from leaking onto portions of the lower substrate except the pixel regions, color filter layers for displaying red, green, and blue colors, and a common electrode.
In general, the LCD device is driven according to optical anisotropy and polarizability of liquid crystal molecules of the liquid crystal material layer. The liquid crystal molecules are aligned due to their long and thin shapes. For example, an electric field is induced to the liquid crystal material layer for controlling alignment directions of the liquid crystal molecules. Accordingly, the alignment directions of the liquid crystal molecules varies, and light is refracted along the alignment directions of the liquid crystal molecules according to the optical anisotropy of the liquid crystal material layer, thereby displaying image data, i.e., a picture.
Presently, active matrix type thin film transistor (TFT) LCD devices have been developed, wherein pixel electrodes for displaying the image data are controlled with a TFT having a semiconductor layer formed on a lower substrate. The active matrix type TFT LCD devices are divided into Inverted Staggered structures and Normal Staggered structures according to locations of gate, source, and drain electrodes. In the Inverted Staggered structure, the gate electrode is formed below the semiconductor layer, and the source and drain electrodes are formed above the semiconductor layer. In the Normal Staggered structure, the gate electrode is formed above the semiconductor layer, and the source and drain electrodes are formed below the semiconductor layer. It is preferred to form the active matrix type TFT LCD device as the Inverted Staggered structure since the Inverted Staggered structure has simplified manufacturing processes, and does not require a TFT black matrix layer.
The Inverted Staggered structure includes a gate electrode on a glass substrate, a gate insulating layer on an entire surface of the substrate including the gate electrode, a semiconductor layer on the gate insulating layer above the gate electrode, source and drain electrodes on the semiconductor layer, and ohmic contact layers interposed between the semiconductor layer and the source and drain electrodes. In the Inverted Staggered structure, an interface between the gate insulating layer and the semiconductor layer is not exposed to the atmosphere. In addition, the gate insulating layer, the semiconductor layer, and the ohmic contact layer may be sequentially deposited on the glass substrate in a single processing chamber, whereby the TFT has improved electrical characteristics, and the ohmic contact layers may be removed above a channel by using the source and drain electrodes as a mask, thereby simplifying manufacturing processes.
FIG. 1 is a plan view of an LCD device according to the related art. In FIG. 1, an LCD device includes a gate line 101, a data line 205, and a pixel electrode 108. In addition, a gate electrode 101a extends from the gate line 101, and the data line including source and drain electrodes 105a and 105b is formed to be perpendicular with the gate line 101. Then, the pixel electrode 108 is formed in a pixel region defined by the gate and data lines 101 and 205 crossing each other. In addition, a semiconductor layer 203, in which a channel region is defined, is formed above the gate electrode 101a, and the source and drain electrodes 105a and 105b are formed at both sides of the channel region of the semiconductor layer 203.
FIGS. 2A to 2G are cross sectional views of manufacturing process steps of the LCD device along I-I′ of FIG. 1 according to the related, and FIGS. 3A to 3G are cross sectional views of manufacturing process steps of the LCD device along II—II of FIG. 1 corresponding to FIGS. 2A to 2G according to the related art. In FIGS. 2A and 3A, a metal layer is deposited on an entire surface of a lower substrate 100 by-sputtering, and then the metal layer is selectively removed in a patterning process using photolithographic processes, thereby forming the gate line (101 of FIG. 1) that extends along a first direction and the gate electrode 101a that extends from the gate line 101.
In FIGS. 2B and 3B, a gate insulating layer 102 is formed on an entire surface of the lower substrate 100 including the gate line 101 and the gate electrode 101a. 
In FIGS. 2C and 3C, the semiconductor layer (203 of FIG. 1) is deposited on the gate insulating layer 102, and then selectively patterned to remain on the gate insulating layer 102 above the gate electrode 101a, thereby forming an active layer of the TFT. In addition, the semiconductor layer (203 in FIG. 1) is formed by sequentially depositing an amorphous silicon layer 103 and an impurity-doped layer 104. In FIG. 3C, the semiconductor layer is not formed above the gate line 101.
In FIGS. 2D and 3D, a metal layer 105 is deposited on an entire surface of the lower substrate 100 including the semiconductor layer 203. After depositing a photoresist on the entire surface of the metal layer 105, a photoresist pattern 106 is formed by exposure and developing processes with a mask for patterning the data line and the source and drain electrodes.
In FIGS. 2E and 3E, the metal layer 105 is selectively etched by using the photoresist pattern 106 as the mask, thereby forming the data line (205 of FIG. 1), wherein the source electrode 105a extends from the data line 205 and the drain electrode 105b is formed apart from the source electrode 105a. In FIG. 3E, a step difference is generated between portions of the lower substrate 100 and the gate line 101. Moreover, the step difference is generated between one portion of the lower substrate 100 having the gate line 101 and the other portion of the lower substrate 100 having no gate line, thereby deteriorating step coverage characteristics of the gate insulating layer 102. As a result, the gate insulating layer 102 is not elaborate. In regions D, some residual metal components of the metal layer 105 penetrate into the gate insulating layer 102 since the metal layer 105 remains along the step difference of the gate insulating layer 102.
In FIG. 2F, the impurity-doped layer 104 that forms the semiconductor layer 203 is removed using the source and drain electrodes 105a and 105b as the mask, thereby forming an ohmic contact layer 104a. At this time, an ashing process is performed before or after selectively removing the impurity-doped layer 104.
In FIG. 2G, a passivation layer is formed on an entire surface of the lower substrate 100 including the source and drain electrodes 105a and 105b, and then selectively removed to expose a predetermined portion of the drain electrode 105b, thereby forming a contact hole. Subsequently, a transparent conductive layer is formed on an entire surface of the lower substrate 100 including the contact hole, and then the pixel electrode 108 is formed electrically connected to the drain electrode 105b through the contact hole by patterning the transparent conductive layer.
In FIG. 3G, the residual metal components of the metal layer 105 are formed within the regions D (in FIG. 3E) that is the step difference of the gate insulating layer 102. The residual metal components remain on the step difference portion during processes for selectively removing the impurity-doped layer 104 in the TFT region (in FIG. 2F), and depositing the passivation layer on an entire surface of the lower substrate. As a result, dark dots may be generated and/or insulating characteristics may be deteriorated. In addition, a passivation layer 107 is formed over the gate insulating layer 102 and the regions D (in FIG. 3E) to reduced the step difference of the gate insulating layer 102.
However, when forming the metal layer of molybdenum Mo, residual amounts of the metal layer remain on the gate insulating layer after patterning of the metal layer. Specifically, in the step difference portion of the gate insulating layer according to the gate line, the residual amounts of the metal layer significantly penetrate into the gate insulating layer, thereby generating the dark dots and deteriorating the insulating characteristics of the gate insulating layer. In addition, it is not possible to remove the residual amounts of the Mo layer during wet-etching for patterning the source and drain electrodes.